Re: Hibernate resume bug around 3,18-rc2 - Full PAT support

[Luis R. Rodriguez]

On Wed, Nov 25, 2015 at 06:01:20AM +0100, Juergen Gross wrote:
> On 24/11/15 23:46, Luis R. Rodriguez wrote:
> > On Mon, Nov 23, 2015 at 03:19:16PM +0100, Juergen Gross wrote:
> >> On 23/11/15 15:11, vasvir@xxxxxxxxxxxxxxxxx wrote:
> >>> Ok I will send the .config when I get back home. I have all kernels I
> >>> build in .deb archive. The problem is that the debian kernel build
> >>> procedure does not hold somewhere in the deb file the git commit hash.
> >>>
> >>> Fow which kernel would you care to see the config? 4.3?
> >>
> >> Doesn't really matter anymore. I've posted a patch already to fix it and
> >> got the reply, that the fix is okay, but no harm can come from the
> >> current implementation, as the two config options are always either both
> >> set or reset.
> > 
> > Hrm, Vassilis seems to be able to reproduce this more effectively by heating up
> > his CPU prior to hibernation though. I have no idea what adding APIC_LVT_MASKED
> > ((1 << 16)) to the Local Vector Table (LVT) Thermal Monitor (APIC_LVTTHMR 0x330) does but
> > clear_local_APIC() seems to be used to "cleanout any BIOS leftovers during
> > boot." If we're suspending but the fan is still on I wonder if this could cause
> > an issue with some settings the BIOS may have set prior to hibernation, and
> > a mismatch upon resume.
> > 
> > I can't find what APIC_LVT_MASKED does though, the best doc I found:
> 
> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf
> 
> Local APIC (chapter 10.4).

Thanks, yeah I only see the same thing you spotted and fixed [0] but also
agree it does not play a role with this issue. Although completely
not documented the APIC_LVT_MASKED just masks the thermal interrupts
while we go down, and we just set the original value of the thermal
register when we come up. The only other possible cautious reading about
the thermal register seemed to be x86-32 bit specific.

Let's see what the bisect ends up with.

[0] https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git/commit/?id=42baa2581c92f8d07e7260506c8d41caf14b0fc3

  Luis
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