[PATCH v3 0/2] perf/x86: fixes and improvements for Intel Atom PEBS/LBR support

[Stephane Eranian]

This short series fixes breakage of Intel Atom PEBS and LBR support in recent kernels.
The problems were introduced with the changes in the PEBS logic to handle deeper buffer.
Refer to the changelog in the specific commits for SHA1.

The first patch fixes LBR assumption that 64-bit LBR format implies LBR_SELECT msr.
The second patch fixes PEBS support and wrong pointer arithmetic and assumption about
Atom/Core2 PEBS record layout.

The third patch adds an alias for cycles:pp to Intel Atom given that perf record/top
uses cycles:pp nowadays.

The fourth patch allows using precise sampling attribute on all events on Intel Atom.
When used on non-PEBS events, no samples are generated. No error is reported, this is
consistent with the behavior for other Intel processors.

In V2, we removed the alias function specific to Atom use use the one from Core2
because it is identical as suggested by Kan Liang.

In V3, we split up the series into 4 patches and referenced the commits which introduced
the issues.

Stephane Eranian (4):
  perf/x86: fix LBR issues on Intel Atom
  perf/x86: fix PEBS issues on Intel Atom/Core2
  perf/x86: enable cycles:pp for Intel Atom
  perf/x86: allow precise mode on all events for Intel Atom

 arch/x86/kernel/cpu/perf_event_intel.c     |  1 +
 arch/x86/kernel/cpu/perf_event_intel_ds.c  | 11 ++++++++++-
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++----
 3 files changed, 18 insertions(+), 5 deletions(-)

-- 
1.9.1

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