Re: [PATCH v5 08/10] spi: expose master transfer size limitation.

[Michal Suchanek]

On 4 December 2015 at 15:30, Martin Sperl <martin@xxxxxxxxx> wrote:
>
>> On 02.12.2015, at 00:12, Mark Brown <broonie@xxxxxxxxxx> wrote:
>>
>> On Tue, Dec 01, 2015 at 04:51:06PM -0000, Michal Suchanek wrote:
>>
>>> +static inline size_t
>>> +spi_max_transfer_size(struct spi_device *spi)
>>> +{
>>> +    struct spi_master *master = spi->master;
>>> +    if (!master->max_transfer_size)
>>> +            return 0;
>>> +    return master->max_transfer_size(spi);
>>> +}
>>
>> Can we change this to return SIZE_MAX instead (ie, the maximum value for
>> a size_t)?  That way callers don't need to worry if there is a limit, if
>> they want to handle it they can just unconditionally assume that a limit
>> will be provided.
>
> As I just came across: spi_master.max_dma_len, so I wonder how this
> value would differ from the proposed spi_master.max_transfer_size
> on specific HW?
>
> For all practical purposes I would assume both are identical.

They aren't.

Some SPI masters don't use DMA. Some SPI master drivers can drive CS
manually so they can glue multiple DMA (or whatever) transfers into
single logical SPI transfer transparently. And some cannot. Hence this
limit.

That said I don't know what is the purpose of spi_master.max_dma_len.
It is seldom used. It seems to be used as a hint for the DMA buffer
size in spi.c only.

It is set in 3 drivers.

Thanks

Michal
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