Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Maxime Ripard]

On Tue, Dec 08, 2015 at 09:06:58AM +0100, Jean-Francois Moine wrote:
> On Mon, 7 Dec 2015 19:44:30 +0100
> Jens Kuske <jenskuske@xxxxxxxxx> wrote:
> 
> > >> +					     "bus_lcd0", "bus_lcd1", "bus_deint",
> > 
> > > 	"bus_tcon0", "bus_tcon1", "bus_deint",
> > > 
> > > (the tcon1 clock is used by both lcd0 and lcd1, while
> > >  the tcon0 clock is used for TV output from lcd1)
> > 
> > Hi,
> > 
> > These are only the ahb bus gates, not the module clocks.
> > Naming them lcd might be a bit confusing, but it follows the naming we
> > used since sun4i. And the tcon modules are still called lcd0 and lcd1
> > module in the manual too.
> 
> There is no reference to TCON0 in the LCDs registers (H3 V1.1 pages 428
> and 435), only TCON1.
> 
> > Interestingly there is only a tcon0 module clock in the manual and no
> > tcon1, but that is not part of this patch.
> 
> Well, I looked again in the 3.4 kernel and, for the LCD0/HDMI, there is
> no clock setting for TCON1: it just receives the AHB1 clock.
> 
> This means that its gate ("bus_lcd1" or "ahb1_tcon1") must be enabled
> when streaming on LCD0 or LCD1.
> 
> The role of tcon0 is not yet clear to me, but it seems that its clock
> is the streaming clock for LCD1/TV, as the HDMI clock is for LCD0/HDMI.

If the H3 display block is done the same way than the A10 (and later)
one on this aspect, then the TCON has two channels with two different
streaming (or functional, you pick the name) clocks. The channel 0 is
usually used for RGB, the channel 1 for HDMI, composite and VGA.

Maybe they just added different bus gates for those two different
channels, and moved HDMI to the channel 0.

Anyway, that can always be changed later on if we have more clue on
what's going on.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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