Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value

[Herbert Xu]

On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote:
> 
> NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
> nothing to do with NX request. Since this bit can be set with other
> valuable return status, mast this bit.
> 
> One of other bits (INITIATED, BUSY or REJECTED) will be returned for
> any given NX request.
> 
> Signed-off-by: Haren Myneni <haren@xxxxxxxxxx>

Patch applied.  Thanks.
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Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
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