Re: [PATCH v2 0/2] Introduce the bulk IV mode for improving the crypto engine efficiency

[Mark Brown]

On Sat, Jan 02, 2016 at 11:46:08PM +0100, Milan Broz wrote:

> Anyway, I think that you should optimize driver, not add strange hw-dependent
> crypto modes to dmcrypt. This is not the first crypto accelerator that is just not
> suited for this kind of use.

> (If it can process batch of chunks of data each with own IV, then it can work
> with dmcrypt, but I think such optimized code should be inside crypto API,
> not in dmcrypt.)

The flip side of this is there is an awful lot of hardware out there
that has basically this pattern and if we can make the difference
between people being able to encrypt or not encrypt their storage due to
performance then that seems like a win.  Getting hardware changes isn't
going to be a fast process.  From a brief look at the crypto layer it
does look there may be things we can do there, if only in terms of
factoring out the common patterns for driving the queue of operations
into the hardware so it's easy for drivers to do the best thing.  

One thing that occurs to me for the IV programming that has been
proposed for SPI by Martin Sparl (and seen good results on Raspberry PI)
is to insert transfers programming the crypto engine into the stream of
DMA operations so we can keep the hardware busy.  It won't work with
every SoC out there but it will work with a lot of them, it's what
hardware that explicitly supports this will be doing internally.  It's
the sort of thing that would benefit from factoring out, it's a lot of
hassle to implement per driver.

The main thing the out of tree req-dm-crypt code is doing was using a
larger block size which does seem like a reasonable thing to allow
people to tune for performance tradeofffs but I undertand that's a lot
harder to achieve in a good way than one might hope.

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