RE: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Subbaraya Sundeep Bhatta]

Hi Soren,

> -----Original Message-----
> From: SÃren Brinkmann [mailto:soren.brinkmann@xxxxxxxxxx]
> Sent: Wednesday, January 13, 2016 9:01 PM
> To: Subbaraya Sundeep Bhatta
> Cc: kishon@xxxxxx; robh@xxxxxxxxxx; balbi@xxxxxx;
> gregkh@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; Subbaraya Sundeep Bhatta
> Subject: Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.
> 
> On Wed, 2016-01-13 at 07:43PM +0530, Subbaraya Sundeep Bhatta wrote:
> > This patch adds the document describing dt bindings for ZynqMP PHY.
> > ZynqMP SOC has a High Speed Processing System Gigabit Transceiver
> > which provides PHY capabilties to USB, SATA, PCIE, Display Port and
> > Ehernet SGMII controllers.
> >
> > Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xxxxxxxxxx>
> 
> I missed the v2 hence again.
> 
> > ---
> >  v2:
> > 	modified to use phy cells as 2.
> >
> >  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103
> +++++++++++++++++++++
> >  1 file changed, 103 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > new file mode 100644
> > index 0000000..975cf21
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > @@ -0,0 +1,103 @@
> > +Xilinx ZynqMP PHY binding
> > +
> > +This binding describes a ZynqMP PHY device that is used to control
> > +ZynqMP High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides
> > +four lanes and are used by USB, SATA, PCIE, Display port and Ethernet
> SGMMI controllers.
> > +
> > +Required properties (controller (parent) node):
> > +- compatible    : Should be "xlnx,zynqmp-psgtr"
> > +
> > +- reg		: Address and length of register sets for each device in
> > +		  "reg-names"
> > +- reg-names     : The names of the register addresses corresponding to the
> > +		  registers filled in "reg":
> > +			- serdes: SERDES block register set
> > +			- siou: SIOU block register set
> > +			- lpd: Low power domain peripherals reset control
> > +			- fpd: Full power domain peripherals reset control
> 
> The reset registers should not be directly modified by Linux. Any access to
> resets is likely requiring a reset controller that uses platform FW to modify the
> resets.

Ok I will fix this and send next iteration.

> > +
> > +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> > +			  termination resistance can be out of spec due to a
> > +			  bug in the calibration logic. This issue will be fixed
> > +			  in silicon in future versions.
> 
> The silicon version is run-time detectable. There should be a way to get away
> without this property.

Ok I will fix this and send next iteration.

Thanks,
Sundeep.
> 
> 	SÃren