Re: [PATCH v1 0/3] clk: rockchip: rk3368: fix some error for rk3368 clk

[Heiko Stübner]

Hi,

Am Montag, 25. Januar 2016, 08:55:59 schrieb Zhang Qing:
> From: zhangqing <zhangqing@xxxxxxxxxxxxxx>
> 
> modify edp_24m parent select bit.
> enable CLK_SET_RATE_PARENT flag for spdif_8ch and i2s_2ch.
> 
> zhangqing (3):
>   clk: rockchip: rk3368: fix edp_24m parent
>   clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for
>     spdif_8ch
>   clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch

applied all 3 to my clk branch for 4.6.

I've modified patches 2+3 to keep the line-alingment (= move the CLK_SET_PARENT 
to the line above). In the clock trees I really like to keep the structure 
identical over all clocks (and thus ignore the 80 column limit in parts) to 
make reading the large lists easier, as now everything always is in the same 
place.


Heiko