[PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding

From: Borislav Petkov
Date: Wed Mar 02 2016 - 05:54:05 EST

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From: Borislav Petkov <bp@xxxxxxx>
Date: Wed, 2 Mar 2016 11:23:13 +0100
Subject: [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding

Merge all IP blocks into a single enum. This allows for easier block
name use later. Drop superfluous "_BLOCK" from the enum names.

Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@xxxxxxx>
---
arch/x86/include/asm/mce.h | 46 +++++++++----------
arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 +++++++----
drivers/edac/mce_amd.c | 88 +++++++++++++++---------------------
3 files changed, 76 insertions(+), 85 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 6f1380064471..4a197cb25593 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -311,37 +311,33 @@ extern void apei_mce_report_mem_error(int corrected,
*/
#ifdef CONFIG_X86_MCE_AMD
enum amd_ip_types {
- SMCA_F17H_CORE_BLOCK = 0, /* Core errors */
- SMCA_DF_BLOCK, /* Data Fabric */
- SMCA_UMC_BLOCK, /* Unified Memory Controller */
- SMCA_PB_BLOCK, /* Parameter Block */
- SMCA_PSP_BLOCK, /* Platform Security Processor */
- SMCA_SMU_BLOCK, /* System Management Unit */
+ SMCA_F17H_CORE = 0, /* Core errors */
+ SMCA_LS, /* - Load Store */
+ SMCA_IF, /* - Instruction Fetch */
+ SMCA_L2_CACHE, /* - L2 cache */
+ SMCA_DE, /* - Decoder unit */
+ RES, /* - Reserved */
+ SMCA_EX, /* - Execution unit */
+ SMCA_FP, /* - Floating Point */
+ SMCA_L3_CACHE, /* - L3 cache */
+
+ SMCA_DF, /* Data Fabric */
+ SMCA_CS, /* - Coherent Slave */
+ SMCA_PIE, /* - Power management, Interrupts, etc */
+
+ SMCA_UMC, /* Unified Memory Controller */
+ SMCA_PB, /* Parameter Block */
+ SMCA_PSP, /* Platform Security Processor */
+ SMCA_SMU, /* System Management Unit */
N_AMD_IP_TYPES
};

struct amd_hwid {
- const char *amd_ipname;
- unsigned int amd_hwid_value;
+ const char *name;
+ unsigned int hwid;
};

-extern struct amd_hwid amd_hwid_mappings[N_AMD_IP_TYPES];
-
-enum amd_core_mca_blocks {
- SMCA_LS_BLOCK = 0, /* Load Store */
- SMCA_IF_BLOCK, /* Instruction Fetch */
- SMCA_L2_CACHE_BLOCK, /* L2 cache */
- SMCA_DE_BLOCK, /* Decoder unit */
- RES, /* Reserved */
- SMCA_EX_BLOCK, /* Execution unit */
- SMCA_FP_BLOCK, /* Floating Point */
- SMCA_L3_CACHE_BLOCK /* L3 cache */
-};
+extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES];

-enum amd_df_mca_blocks {
- SMCA_CS_BLOCK = 0, /* Coherent Slave */
- SMCA_PIE_BLOCK /* Power management, Interrupts, etc */
-};
#endif
-
#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 3188cd9eb9b5..c184c92a00ab 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -72,16 +72,25 @@ static const char * const th_names[] = {
};

/* Define HWID to IP type mappings for Scalable MCA */
-struct amd_hwid amd_hwid_mappings[] =
-{
- [SMCA_F17H_CORE_BLOCK] = { "f17h_core", 0xB0 },
- [SMCA_DF_BLOCK] = { "data fabric", 0x2E },
- [SMCA_UMC_BLOCK] = { "UMC", 0x96 },
- [SMCA_PB_BLOCK] = { "param block", 0x5 },
- [SMCA_PSP_BLOCK] = { "PSP", 0xFF },
- [SMCA_SMU_BLOCK] = { "SMU", 0x1 },
+struct amd_hwid amd_hwids[] =
+{
+ [SMCA_F17H_CORE] = { "F17h core", 0xB0 },
+ [SMCA_LS] = { "Load-Store", 0x0 },
+ [SMCA_IF] = { "IFetch", 0x0 },
+ [SMCA_L2_CACHE] = { "L2 Cache", 0x0 },
+ [SMCA_DE] = { "Decoder", 0x0 },
+ [SMCA_EX] = { "Execution", 0x0 },
+ [SMCA_FP] = { "Floating Point", 0x0 },
+ [SMCA_L3_CACHE] = { "L3 Cache", 0x0 },
+ [SMCA_DF] = { "Data Fabric", 0x2E },
+ [SMCA_CS] = { "Coherent Slave", 0x0 },
+ [SMCA_PIE] = { "PwrMan/Intr", 0x0 },
+ [SMCA_UMC] = { "UMC", 0x96 },
+ [SMCA_PB] = { "Param Block", 0x5 },
+ [SMCA_PSP] = { "PSP", 0xFF },
+ [SMCA_SMU] = { "SMU", 0x1 },
};
-EXPORT_SYMBOL_GPL(amd_hwid_mappings);
+EXPORT_SYMBOL_GPL(amd_hwids);

static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 6820d17fea9c..0f9953cbde4e 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -820,58 +820,51 @@ static void decode_mc6_mce(struct mce *m)
pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
}

-static void decode_f17h_core_errors(u8 xec, unsigned int mca_type)
+static void decode_f17h_core_errors(const char *ip_name, u8 xec, unsigned int mca_type)
{
const char * const *error_desc_array;
- char *ip_name;
size_t len;

+ pr_emerg(HW_ERR "%s Error: ", ip_name);
+
switch (mca_type) {
- case SMCA_LS_BLOCK:
+ case SMCA_LS:
error_desc_array = f17h_ls_mce_desc;
- ip_name = "LS";
len = ARRAY_SIZE(f17h_ls_mce_desc) - 1;

if (xec == 0x4) {
pr_cont("Unrecognized error code from LS MCA bank\n");
return;
}
-
break;

- case SMCA_IF_BLOCK:
+ case SMCA_IF:
error_desc_array = f17h_if_mce_desc;
- ip_name = "IF";
len = ARRAY_SIZE(f17h_if_mce_desc) - 1;
break;

- case SMCA_L2_CACHE_BLOCK:
+ case SMCA_L2_CACHE:
error_desc_array = f17h_l2_mce_desc;
- ip_name = "L2_Cache";
len = ARRAY_SIZE(f17h_l2_mce_desc) - 1;
break;

- case SMCA_DE_BLOCK:
+ case SMCA_DE:
error_desc_array = f17h_de_mce_desc;
- ip_name = "DE";
len = ARRAY_SIZE(f17h_de_mce_desc) - 1;
break;

- case SMCA_EX_BLOCK:
+ case SMCA_EX:
error_desc_array = f17h_ex_mce_desc;
- ip_name = "EX";
len = ARRAY_SIZE(f17h_ex_mce_desc) - 1;
break;

- case SMCA_FP_BLOCK:
+ case SMCA_FP:
error_desc_array = f17h_fp_mce_desc;
- ip_name = "FP";
len = ARRAY_SIZE(f17h_fp_mce_desc) - 1;
break;

- case SMCA_L3_CACHE_BLOCK:
+ case SMCA_L3_CACHE:
error_desc_array = f17h_l3_mce_desc;
- ip_name = "L3_Cache";
len = ARRAY_SIZE(f17h_l3_mce_desc) - 1;
break;

@@ -881,7 +874,7 @@ static void decode_f17h_core_errors(u8 xec, unsigned int mca_type)
}

if (xec > len) {
- pr_cont("Unrecognized error code from %s MCA bank\n", ip_name);
+ pr_cont("Unrecognized error code from %s MCA bank\n", amd_hwids[mca_type].name);
return;
}

@@ -891,19 +884,18 @@ static void decode_f17h_core_errors(u8 xec, unsigned int mca_type)
static void decode_df_errors(u8 xec, unsigned int mca_type)
{
const char * const *error_desc_array;
- char *ip_name;
size_t len;

+ pr_emerg(HW_ERR "Data Fabric Error: ");
+
switch (mca_type) {
- case SMCA_CS_BLOCK:
+ case SMCA_CS:
error_desc_array = f17h_cs_mce_desc;
- ip_name = "CS";
len = ARRAY_SIZE(f17h_cs_mce_desc) - 1;
break;

- case SMCA_PIE_BLOCK:
+ case SMCA_PIE:
error_desc_array = f17h_pie_mce_desc;
- ip_name = "PIE";
len = ARRAY_SIZE(f17h_pie_mce_desc) - 1;
break;

@@ -913,7 +905,7 @@ static void decode_df_errors(u8 xec, unsigned int mca_type)
}

if (xec > len) {
- pr_cont("Unrecognized error code from %s MCA bank\n", ip_name);
+ pr_cont("Unrecognized error code from %s MCA bank\n", amd_hwids[mca_type].name);
return;
}

@@ -928,7 +920,7 @@ static void decode_smca_errors(struct mce *m)
unsigned int hwid, mca_type, i;
u8 xec = XEC(m->status, xec_mask);
const char * const *error_desc_array;
- char *ip_name;
+ const char *ip_name;
size_t len;

if (rdmsr_safe(addr, &low, &high)) {
@@ -947,41 +939,39 @@ static void decode_smca_errors(struct mce *m)
* Note: mca_type values make sense only
* in the context of an hwid
*/
- for (i = 0; i < ARRAY_SIZE(amd_hwid_mappings); i++)
- if (amd_hwid_mappings[i].amd_hwid_value == hwid)
+ for (i = 0; i < ARRAY_SIZE(amd_hwids); i++)
+ if (amd_hwids[i].hwid == hwid)
break;

switch (i) {
- case SMCA_F17H_CORE_BLOCK:
- ip_name = (mca_type == SMCA_L3_CACHE_BLOCK) ?
- "L3 Cache" : "F17h Core";
+ case SMCA_F17H_CORE:
+ ip_name = (mca_type == SMCA_L3_CACHE) ?
+ "L3 Cache" : "F17h Core";
+
+ return decode_f17h_core_errors(ip_name, xec, mca_type);
break;

- case SMCA_DF_BLOCK:
- ip_name = "DF";
+ case SMCA_DF:
+ return decode_df_errors(xec, mca_type);
break;

- case SMCA_UMC_BLOCK:
+ case SMCA_UMC:
error_desc_array = f17h_umc_mce_desc;
- ip_name = "UMC";
len = ARRAY_SIZE(f17h_umc_mce_desc) - 1;
break;

- case SMCA_PB_BLOCK:
+ case SMCA_PB:
error_desc_array = f17h_pb_mce_desc;
- ip_name = "PB";
len = ARRAY_SIZE(f17h_pb_mce_desc) - 1;
break;

- case SMCA_PSP_BLOCK:
+ case SMCA_PSP:
error_desc_array = f17h_psp_mce_desc;
- ip_name = "PSP";
len = ARRAY_SIZE(f17h_psp_mce_desc) - 1;
break;

- case SMCA_SMU_BLOCK:
+ case SMCA_SMU:
error_desc_array = f17h_smu_mce_desc;
- ip_name = "SMU";
len = ARRAY_SIZE(f17h_smu_mce_desc) - 1;
break;

@@ -990,20 +980,16 @@ static void decode_smca_errors(struct mce *m)
return;
}

- pr_emerg(HW_ERR "%s Error: ", ip_name);
+ ip_name = amd_hwids[mca_type].name;

- if (i == SMCA_F17H_CORE_BLOCK) {
- decode_f17h_core_errors(xec, mca_type);
- } else if (i == SMCA_DF_BLOCK) {
- decode_df_errors(xec, mca_type);
- } else {
- if (xec > len) {
- pr_cont("Unrecognized error code from %s MCA bank\n", ip_name);
- return;
- }
+ pr_emerg(HW_ERR "%s Error: ", ip_name);

- pr_cont("%s.\n", error_desc_array[xec]);
+ if (xec > len) {
+ pr_cont("Unrecognized error code from %s MCA bank\n", ip_name);
+ return;
}
+
+ pr_cont("%s.\n", error_desc_array[xec]);
}

--
2.3.5

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.

Next message: Laxman Dewangan: "[PATCH] regulator: DT: Add DT property for active-discharge configuration"
Previous message: Borislav Petkov: "[PATCH 1/3] x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors"
In reply to: Borislav Petkov: "[PATCH 1/3] x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors"
Next in thread: Aravind Gopalakrishnan: "Re: [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding"
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