[tip:perf/core] perf/x86/intel: Add definition for PT PMI bit

[tip-bot for Stephane Eranian]

Commit-ID:  5690ae28e472d25e330ad0c637a5cea3fc39fb32
Gitweb:     http://git.kernel.org/tip/5690ae28e472d25e330ad0c637a5cea3fc39fb32
Author:     Stephane Eranian <eranian@xxxxxxxxxx>
AuthorDate: Thu, 3 Mar 2016 20:50:40 +0100
Committer:  Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Tue, 8 Mar 2016 12:18:34 +0100

perf/x86/intel: Add definition for PT PMI bit

This patch adds a definition for GLOBAL_OVFL_STATUS bit 55
which is used with the Processor Trace (PT) feature.

Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Cc: <stable@xxxxxxxxxxxxxxx>
Cc: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx>
Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: Vince Weaver <vincent.weaver@xxxxxxxxx>
Cc: adrian.hunter@xxxxxxxxx
Cc: kan.liang@xxxxxxxxx
Cc: namhyung@xxxxxxxxxx
Link: http://lkml.kernel.org/r/1457034642-21837-2-git-send-email-eranian@xxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
 arch/x86/include/asm/perf_event.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 7bcb861..5a2ed3e 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -165,6 +165,7 @@ struct x86_pmu_capability {
 #define GLOBAL_STATUS_ASIF				BIT_ULL(60)
 #define GLOBAL_STATUS_COUNTERS_FROZEN			BIT_ULL(59)
 #define GLOBAL_STATUS_LBRS_FROZEN			BIT_ULL(58)
+#define GLOBAL_STATUS_TRACE_TOPAPMI			BIT_ULL(55)
 
 /*
  * IBS cpuid feature detection