[added to the 4.1 stable tree] libata: Align ata_device's id on a cacheline

From: Sasha Levin
Date: Sun Mar 13 2016 - 13:46:24 EST

From: Harvey Hunt <harvey.hunt@xxxxxxxxxx>

This patch has been added to the 4.1 stable tree. If you have any
objections, please let us know.


[ Upstream commit 4ee34ea3a12396f35b26d90a094c75db95080baa ]

The id buffer in ata_device is a DMA target, but it isn't explicitly
cacheline aligned. Due to this, adjacent fields can be overwritten with
stale data from memory on non coherent architectures. As a result, the
kernel is sometimes unable to communicate with an ATA device.

Fix this by ensuring that the id buffer is cacheline aligned.

This issue is similar to that fixed by Commit 84bda12af31f
("libata: align ap->sector_buf").

Signed-off-by: Harvey Hunt <harvey.hunt@xxxxxxxxxx>
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: <stable@xxxxxxxxxxxxxxx> # 2.6.18
Signed-off-by: Tejun Heo <tj@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sasha.levin@xxxxxxxxxx>
include/linux/libata.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/libata.h b/include/linux/libata.h
index e0e3378..11c2dd1 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -717,7 +717,7 @@ struct ata_device {
union {
u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */
- };
+ } ____cacheline_aligned;

/* DEVSLP Timing Variables from Identify Device Data Log */
u8 devslp_timing[ATA_LOG_DEVSLP_SIZE];