Re: [PATCH 2/3] x86/topology: Fix AMD core count
From: Huang Rui
Date: Mon Mar 21 2016 - 06:05:15 EST
On Mon, Mar 21, 2016 at 09:23:41AM +0100, Borislav Petkov wrote:
> On Mon, Mar 21, 2016 at 11:07:46AM +0800, Huang Rui wrote:
> > OK, we will find some fam15h, fam16h platforms to verify it. Please
> > wait for my feedback.
> >
> > But I am confused with c->x86_max_cores /= smp_num_siblings, what is
> > the real meaning of c->x86_max_cores here for AMD, the whole compute
> > unit numbers per socket?
>
> Yes, it is the cores and each core can contain two or more logical
> threads. In AMD speak, that's the compute unit count. We read it in
> detect_ht() from CPUID(1).EBX[23:16] which is LogicalProcessorCount,
> i.e., CPUID(8000_0008).ECX[NC] + 1, i.e., the number of cores. And
> "cores" in BKDG speak is the number of all cores in a processor which
> are distributed across compute units....
>
> That's why we divide by the number of siblings, i.e., the number of
> cores in a CU, in AMD speak.
>
> I know, it is confusing but once we're fine with the nomenclature, it'll
> become as clear as day. :-)
>
OK, actually, there was a topology bug on Carrzio before, the thread
number was detected as 1:
Before:
autotest@autotest-Gardenia88:~$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 21
Model: 96
Model name: AMD Eng Sample: ZM1810C1Y4381_34/18/12/06_9874
Stepping: 0
CPU MHz: 1400.000
CPU max MHz: 1800.0000
CPU min MHz: 1400.0000
BogoMIPS: 3592.19
Virtualization: AMD-V
L1d cache: 32K
L1i cache: 64K
L2 cache: 1024K
NUMA node0 CPU(s): 0-3
Now:
ray@hr-ub:~/tip$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 2
Core(s) per socket: 2
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 21
Model: 96
Stepping: 0
CPU MHz: 1400.000
BogoMIPS: 3592.19
Virtualization: AMD-V
L1d cache: 32K
L1i cache: 96K
L2 cache: 1024K
NUMA node0 CPU(s): 0-3
Looks better. I will test it on fam16h machine tomorrow, if it's OK,
will add my Test-by.
Thanks,
Rui