Re: regmap: mmio: regression in pre-v4.6-rc1

[Alexander Stein]

On Wednesday 23 March 2016 11:39:39, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 12:16:13PM +0100, Alexander Stein wrote:
> > On Wednesday 23 March 2016 10:34:15, Mark Brown wrote:
> 
> > > Are you *sure* that this is actually big endian?  Are you basing this on
> > > documentation or on what happened to work for you in the past.
> 
> > Please refer to QorIQ LS1021A Reference Manual (REV 0) table 2.2 (CCSR block 
> > base address map) which states that this peripheral (among _most_ but not all) 
> > requires byte swapping. Same for DSPI.
> > Yeah, it sounds strange.
> 
> I don't have that document.

Nothing wrong with that, I just wanted to state where it is actually documented.

> > > Have you tried tracing through the code to see what ends up happening to
> > > the I/O?  It should come out using your architecture's big endian
> > > accessors.
> 
> > In regmap_mmio_gen_context ctx->reg_read is set to regmap_mmio_read32le and 
> > ctx->reg_write to regmap_mmio_write32le respectively.
> 
> So how does that happen then?  We set these values if the bus is
> default, little or native endian but if it's big endian we go into a
> completely different case...

Well, in regmap_mmio_gen_context config->reg_format_endian is still set to REGMAP_ENDIAN_DEFAULT. of_syscon_register sets config.val_format_endian (notice val_ instead of reg_) depending on "big-endian" (or "little-endian") property.
I'm kinda confused regarding reg_format_endian and val_format_endian. Dunno what should be set in which way.

Best regards,
Alexander