Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller

From: Xing Zheng
Date: Sun Mar 27 2016 - 23:25:51 EST

Hi Heiko,

On 2016å03æ28æ 08:07, Heiko Stuebner wrote:
Hi Xing,

Am Montag, 28. MÃrz 2016, 01:52:12 schrieb Heiko StÃbner:
Am Samstag, 26. MÃrz 2016, 14:37:54 schrieb Xing Zheng:
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Xing Zheng<zhengxing@xxxxxxxxxxxxxx>
Signed-off-by: Jianqun Xu<jay.xu@xxxxxxxxxxxxxx>
Acked-by: Rob Herring<robh@xxxxxxxxxx>

Changes in v5: None
Changes in v3: None
Changes in v2: None

.../bindings/clock/rockchip,rk3399-cru.txt | 83

++++++++++++++++++++ 1 file changed, 83 insertions(+)

create mode 100644


diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-

b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
file mode 100644
index 0000000..9427caa
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,83 @@
+* Rockchip RK3399 Clock and Reset Unit
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for
SoC +peripherals.
+Required Properties:
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory

+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+Optional Properties:
+- rockchip,grf: phandle to the syscon managing the "general register

+ If missing, pll rates are not changeable, due to the missing pll lock
status. +
the rk3399 doesn't need the GRF, so we should drop this block for now
actually, I just saw that the GRF is needed for the static settings during
init. So the rockchip,grf should stay but also move up to required

Same for the grf-comment in the examples-section.

I check the setting of the pclk_alive and pclk_pmu_src are not gating default on the PMUGRF_SOC_CON0,
so I think that we don't need to do the static settings to re-enable them in the clock driver any more.


- Xing Zheng