Re: [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399

[Xing Zheng]

Hi Heiko,

On 2016å03æ28æ 08:13, Heiko Stuebner wrote:
> Hi Xing,
>
> Am Samstag, 26. MÃrz 2016, 14:37:56 schrieb Xing Zheng:
> > Add the clock tree definition for the new RK3399 SoC.
> >
> > Signed-off-by: Xing Zheng<zhengxing@xxxxxxxxxxxxxx>
> > ---
> [...]
>
> > +	/*
> > +	 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in
> > system, +	 * so we ignore the mux and make clocks nodes as following,
> > +	 *
> > +	 * pclkin_cifinv --|-------\
> > +	 *                 |GSC20_9|-- pclkin_cifmux
> > +	 * pclkin_cif    --|-------/
> > +	 */
> > +	GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cifmux",
> please name that source clock pclkin_cif as in the TRM.
> pclkin_cif is the actual input clock - if I'm reading the TRM correctly and
> the inverter is part of the soc or so?
>
> That we currently hide / hardcode the phase-handling should not be part of
> our outside connection - which should be stable even if we implement this
> later.
Yes, I think I will modify them like this:

GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(27), 6, GFLAGS),

Thanks.

--
- Xing Zheng