Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

From: Matthew McClintock
Date: Mon Mar 28 2016 - 16:41:07 EST

On Mar 28, 2016, at 1:13 PM, Guenter Roeck <linux@xxxxxxxxxxxx> wrote:
>>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
>>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
>>> undefined.
>> I honestly donât see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts.
> That is from the APQ8064 datasheet.

So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?