Re: [PATCH] regmap: mmio: Fix value endianness selection

From: Stefan Agner
Date: Tue Mar 29 2016 - 02:14:23 EST

On 2016-03-28 23:10, Alexander Stein wrote:
> On Friday 25 March 2016 11:24:59, Mark Brown wrote:
>> On Wed, Mar 23, 2016 at 03:20:46PM +0100, Alexander Stein wrote:
>> > The difference in those drivers is that syscon manually sets
>> > config.val_format_endian before calling regmap_init_mmio.
>> > spi-fsl-dspi does not. I guess this driver relies on this configuration
>> > being done in regmap_get_val_endian. But this is never reached because
>> > after setting
>> Does this IP exist in configurations where it is anything other than big
>> endian? If not then this probably shouldn't be in DT.
> AFAIK it is included once or twice in the VFxxx series. CC'ed Stefan Agner for
> confirmation.
> Stefan: Is the DCU on VFxxx attached little-endian, e.g. no byte swapping
> needed when accessing the periphery?

Yes, DCU as well as DSPI is attached little endian on Vybrid (aka.