Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
From: Thomas Petazzoni
Date: Thu Mar 31 2016 - 16:37:49 EST
On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote:
> From: Jisheng Zhang <jszhang@xxxxxxxxxxx>
> Date: Wed, 30 Mar 2016 19:55:21 +0800
> > The mvneta is also used in some Marvell berlin family SoCs which may
> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
> > usage with L1_CACHE_BYTES.
> > And since dma_alloc_coherent() is always cacheline size aligned, so
> > remove the align checks.
> > Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxxx>
A new version of the patch was sent, which more rightfully uses
"[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size"
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering