Re: [PATCH v3 6/7] x86/cpu: Add Erratum 88 detection on AMD
From: Andy Lutomirski
Date: Thu Apr 07 2016 - 21:40:44 EST
On Thu, Apr 7, 2016 at 5:31 PM, Andy Lutomirski <luto@xxxxxxxxxx> wrote:
> From: Borislav Petkov <bp@xxxxxxx>
>
> Erratum 88 affects old AMD K8s, where a SWAPGS fails to cause an input
> dependency on GS. Therefore, we need to MFENCE before it.
>
> But that MFENCE is expensive and unnecessary on the remaining x86 CPUs
> out there so patch it out on the CPUs which don't require it.
This is basically identical to:
https://lkml.kernel.org/g/1458576969-13309-4-git-send-email-andi@xxxxxxxxxxxxxx
Whoops! I thought I'd seen that somewhere but I couldn't spot it.
Ingo, etc: we should probably apply one of those patches with a
-stable tag (to mitigate the otherwise potentially unpleasant
performance regression in here), but I don't really care which one.
Andi's has a name for the bug that seems nicer by one character to me,
but it would have to be (trivally) rebased.
--Andy
>
> Signed-off-by: Borislav Petkov <bp@xxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Signed-off-by: Andy Lutomirski <luto@xxxxxxxxxx
> ---
> arch/x86/entry/entry_64.S | 2 +-
> arch/x86/include/asm/cpufeatures.h | 2 ++
> arch/x86/kernel/cpu/amd.c | 1 +
> 3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
> index 858b555e274b..64d2033d1e49 100644
> --- a/arch/x86/entry/entry_64.S
> +++ b/arch/x86/entry/entry_64.S
> @@ -783,7 +783,7 @@ ENTRY(native_load_gs_index)
> SWAPGS
> gs_change:
> movl %edi, %gs
> -2: mfence /* workaround */
> +2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
> SWAPGS
> popfq
> ret
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 2a052302bc43..7bfb6b70c745 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -295,6 +295,8 @@
> #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
> #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
> #define X86_BUG_NULL_SEG X86_BUG(9) /* Nulling a selector preserves the base */
> +#define X86_BUG_SWAPGS_FENCE X86_BUG(10) /* SWAPGS without input dep on GS */
> +
>
> #ifdef CONFIG_X86_32
> /*
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index 6e47e3a916f1..b7cc9efe08b5 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -632,6 +632,7 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
> */
> msr_set_bit(MSR_K7_HWCR, 6);
> #endif
> + set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
> }
>
> static void init_amd_gh(struct cpuinfo_x86 *c)
> --
> 2.5.5
>
--
Andy Lutomirski
AMA Capital Management, LLC