Re: [RESEND PATCH v9] mtd: spi-nor: add hisilicon spi-nor flash controller driver

[Jiancheng Xue]

Hi,

On 2016/4/8 18:04, Marek Vasut wrote:
> On 04/08/2016 10:26 AM, Jiancheng Xue wrote:
>> Hi,
>>
>> On 2016/4/7 10:28, Marek Vasut wrote:
>>> On 04/07/2016 04:10 AM, Jiancheng Xue wrote:
>>>> Hi Brian,
>>>>    Thank you very much for your comments. I'll fix these issues in next version.
>>>> In addition, for easy understanding I'd like to rewrite hisi_spi_nor_write and
>>>> hisi_spi_nor_read. Your comments on these modifications will be highly appreciated.
>>>
>>> Would you please stop top-posting ? It rubs some people the wrong way.
>>>
>> I feel very sorry about that. I have read the etiquette and won't make the same mistake again.
>>
>>>> static int hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
>>>> 		size_t *retlen, u_char *read_buf)
>>>> {
>>>> 	struct hifmc_priv *priv = nor->priv;
>>>> 	struct hifmc_host *host = priv->host;
>>>> 	int i;
>>>>
>>>> 	/* read all bytes in only one time */
>>>> 	if (len <= HIFMC_DMA_MAX_LEN) {
>>>> 		hisi_spi_nor_dma_transfer(nor, from, host->dma_buffer,
>>>> 				len, FMC_OP_READ);
>>>> 		memcpy(read_buf, host->buffer, len);
>>>
>>> Is all the ad-hoc memcpying necessary? I think you can use
>>> dma_map_single() and co to obtain DMAble memory for your
>>> controller's use and then you can probably get rid of most
>>> of this stuff.
>>>
>> Considering read_buf >= high_mem case, I think it is also complicated to use dma_map_*
>> and the DMA buffer allocated by the driver is still needed. But I am not sure about
>> this. Please let me know if I am wrong. Thank you!
> 
> Does your controller/DMA have a limitation where it's buffers must be in
> the bottom 4GiB range ? The DMA framework should be able to take care of
> such platform limitations.
> 
When read_buf is allocated by vmalloc, the underlying physical memory may be not contiguous.
In this case, dma_map_single can't be used directly. I think inner DMA buffer and memcpy are still
needed. Am I right?

Regards,
Jiancheng.