Re: [PATCH RFC 0/8] mtd: spi-nor: fix support of Quad SPI memories

[Marek Vasut]

On 04/13/2016 07:23 PM, Cyrille Pitchen wrote:
> Hi all,
> 
> this series is RFC but has already been tested on a sama5d2x xplained
> board with the Atmel QSPI controller + Micron n25q128a13:
> compatible = "micron,n25q128a13", "jedec,spi-nor";
> 
> This first 3 patches of the series are stable and have already been
> submitted to linux-mtd. They are required as a base for the later
> patches.
> 
> Support of Micron memories has been implemented as an example, other
> memory entries should be updated as needed in the spi_nor_ids[] table.
> 
> This new way to support Quad SPI memories is inspired by the JEDEC
> SFDP standard. However SFDP tables are not provided by all memories and
> some of them badly implement the standard. Also the standard itself
> can tell whether the memory supports the 2-2-2 mode but doesn't provide
> the procedure to enter/leave this mode as provided for the 4-4-4 mode.
> 
> 
> Please note that some commit messages are missing but a review might be
> really helpfull! :)
> 
> Almost all the actual rework is done in patch 4.

For Altera SoCFPGA , Cadence QSPI NOR controller , Terasic SoCkit board:
Tested-by: Marek Vasut <marex@xxxxxxx>

Best regards,
Marek Vasut