On 04/18/2016 02:46 AM, Laxman Dewangan wrote:
+
+ /* There is only one debounce count register per port and hence
+ * set the maximum of current and requested debounce time.
+ */
+ max_dbc = tegra_gpio_readl(GPIO_DBC_CNT(offset));
What if the system boots with random values in that register, or some code that runs before the kernel programs large values into the register? That would (incorrectly) impose a lower bound on the possible values the kernel driver can impose. Perhaps the kernel should clear the DBC_CNT registers at probe(), or should store a shadow copy of the DBC_CNT register, use that value here rather than re-reading the registers, and clear that SW shadow at probe().
+ max_dbc = max(max_dbc, debounce_ms);
I wonder if there should be more discussion of how to honor conflicting requests. Perhaps we should only allow exactly equal values (someone might strictly care about latency, and increasing the latency of GPIO X1 just because GPIO X5 wanted a longer debounce period might not be acceptable). Does the GPIO subsystem define explicit semantics for this case?
+ tegra_gpio_mask_write(GPIO_MSK_DBC_EN(offset), offset, 1);
+ tegra_gpio_writel(max_dbc, GPIO_DBC_CNT(offset));
I think DBC_CNT should be written first; the debounce process uses that data to configure itself. The process shouldn't be enabled before it's configured.