[PATCH] ppc64: allow ptrace to set TM bits

[Laurent Dufour]

This patch allows the MSR bits relative to the Transactional memory
state to be manipulated through the ptrace API.

However, in the case the TM available bit is not set in the
manipulated MSR, the changes are ignored.

When dealing with the checkpointed MSR, we must be sure that the TM
state bits will not be set since the checkpointed state can't be a
transactional one.

Signed-off-by: Laurent Dufour <ldufour@xxxxxxxxxxxxxxxxxx>
---
 arch/powerpc/kernel/ptrace.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index b063fc499c1d..5c792f0bf1ca 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -161,8 +161,12 @@ const char *regs_query_register_name(unsigned int offset)
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 #define MSR_DEBUGCHANGE	0
 #else
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+#define MSR_DEBUGCHANGE	(MSR_TS_MASK | MSR_SE | MSR_BE)
+#else
 #define MSR_DEBUGCHANGE	(MSR_SE | MSR_BE)
 #endif
+#endif
 
 /*
  * Max register writeable via put_reg
@@ -180,6 +184,12 @@ static unsigned long get_user_msr(struct task_struct *task)
 
 static int set_user_msr(struct task_struct *task, unsigned long msr)
 {
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (!(task->thread.regs->msr & MSR_TM)) {
+		/* If TM is not available, discard TM bits changes */
+		msr &= ~(MSR_TM | MSR_TS_MASK);
+	}
+#endif
 	task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
 	task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
@@ -193,6 +203,7 @@ static unsigned long get_user_ckpt_msr(struct task_struct *task)
 
 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
 {
+	msr &= ~MSR_TS_MASK;	/* Checkpoint state can't be in transaction */
 	task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
 	task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
-- 
1.9.1


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