Re: [RFC 0/7] iio: inv_mpu6050: Support i2c master and external readings

From: Mark Brown
Date: Tue May 03 2016 - 07:32:19 EST

On Tue, May 03, 2016 at 02:21:40PM +0300, Crestez Dan Leonard wrote:

> I have a device which has several registers with bits that are a mix of
> "cacheable" and "volatile". For example for register SLV4_CTRL:

> - Bit 7 (I2C_SLV4_EN) triggers a transaction with slave 4 when a "1" is
> written. The bit is cleared when the transaction is done.
> - Bits 0-4 (I2C_MST_DLY) configures the reduced access rate of I2C
> slaves relative to the device sample rate. This applies to slaves 0-3 as
> well.

> If I2C_MST_DLY was a separate register it could be easily cached by
> regmap. Because it's part of a volatile register I have to add a
> private_data field caching the value and always write it when triggering
> a SLV4 transfer.

> Jonathan was wondering if regmap can still be used somehow instead of
> custom caching.

If you want to cache in regmap just write a 0 back to the enable bit
after you've set it.

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