From: Yongji XieSo you mean critical registers in same MMIO BAR as MSI-X
Sent: Tuesday, May 03, 2016 3:34 PM
On 2016/5/3 14:22, Tian, Kevin wrote:
We want to allow the MSI-X table because there may beFrom: Yongji Xie [mailto:xyjxie@xxxxxxxxxxxxxxxxxx]A bit confused here. If guest kernel doesn't need to write
Sent: Tuesday, May 03, 2016 2:08 PM
On 2016/5/3 13:34, Tian, Kevin wrote:
Here we just allow to mmap MSI-X table in kernel. It doesn'tFrom: Yongji XieA curious question here. Does "allow to mmap MSI-X" essentially
Sent: Wednesday, April 27, 2016 8:43 PM
This patch enables mmapping MSI-X tables if hardware supports
interrupt remapping which can ensure that a given pci device
can only shoot the MSIs assigned for it.
With MSI-X table mmapped, we also need to expose the
read/write interface which will be used to access MSI-X table.
Signed-off-by: Yongji Xie <xyjxie@xxxxxxxxxxxxxxxxxx>
mean that KVM guest can directly read/write physical MSI-X
mean all KVM guest can directly read/write physical MSI-X
structure. This should be decided by QEMU. For PPC64
platform, we would allow to passthrough the MSI-X table
because we know guest kernel would not write physical
MSI-X structure when enabling MSI.
physical MSI-X structure, what's the point of passing through
the table then?
some critical registers in the same page as the MSI-X table.
We have to handle the mmio access to these register in QEMU
rather than in guest if mmapping MSI-X table is disallowed.
table, instead of two MMIO BARs in same page (the latter I
suppose with your whole patchset it won't happen then)?