RE: [PATCH V2 1/2] perf/x86/intel/uncore: Add support for Intel SKL client uncore

[Liang, Kan]

Hi Thomas and Peter,

Any comments for the patch series?

Thanks,
Kan

> 
> From: Kan Liang <kan.liang@xxxxxxxxx>
> 
> This patch addes full support for Intel SKL client uncore.
>  - Add support for SKL client cpu uncore, which is similar to BDW
>    client. There are some differences in CBOX number and uncore control
>    MSR.
>  - Add new CPU model 78 for SkyLake Mobile, include both cpu and pci
>    uncore.
> 
> Signed-off-by: Kan Liang <kan.liang@xxxxxxxxx>
> ---
> 
> Changes since V1:
>  - Move enable_box to another patch.
>  - Remove disable_box
> 
>  arch/x86/events/intel/uncore.c     |  4 ++-
>  arch/x86/events/intel/uncore.h     |  1 +
>  arch/x86/events/intel/uncore_snb.c | 67
> +++++++++++++++++++++++++++++++++++++-
>  3 files changed, 70 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index 16c1789..7fe2f77 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -1361,6 +1361,7 @@ static const struct intel_uncore_init_fun
> knl_uncore_init __initconst = {  };
> 
>  static const struct intel_uncore_init_fun skl_uncore_init __initconst = {
> +	.cpu_init = skl_uncore_cpu_init,
>  	.pci_init = skl_uncore_pci_init,
>  };
> 
> @@ -1384,7 +1385,8 @@ static const struct x86_cpu_id intel_uncore_match[]
> __initconst = {
>  	X86_UNCORE_MODEL_MATCH(79, bdx_uncore_init),	/* BDX-EP */
>  	X86_UNCORE_MODEL_MATCH(86, bdx_uncore_init),	/* BDX-DE */
>  	X86_UNCORE_MODEL_MATCH(87, knl_uncore_init),	/* Knights
> Landing */
> -	X86_UNCORE_MODEL_MATCH(94, skl_uncore_init),	/* SkyLake */
> +	X86_UNCORE_MODEL_MATCH(78, skl_uncore_init),	/* SkyLake
> Mobile */
> +	X86_UNCORE_MODEL_MATCH(94, skl_uncore_init),	/* SkyLake
> Desktop */
>  	{},
>  };
> 
> diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
> index 79766b9..798cd89 100644
> --- a/arch/x86/events/intel/uncore.h
> +++ b/arch/x86/events/intel/uncore.h
> @@ -360,6 +360,7 @@ int bdw_uncore_pci_init(void);  int
> skl_uncore_pci_init(void);  void snb_uncore_cpu_init(void);  void
> nhm_uncore_cpu_init(void);
> +void skl_uncore_cpu_init(void);
>  int snb_pci2phy_map_init(int devid);
> 
>  /* perf_event_intel_uncore_snbep.c */
> diff --git a/arch/x86/events/intel/uncore_snb.c
> b/arch/x86/events/intel/uncore_snb.c
> index 96531d2..97a69db 100644
> --- a/arch/x86/events/intel/uncore_snb.c
> +++ b/arch/x86/events/intel/uncore_snb.c
> @@ -1,4 +1,4 @@
> -/* Nehalem/SandBridge/Haswell uncore support */
> +/* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */
>  #include "uncore.h"
> 
>  /* Uncore IMC PCI IDs */
> @@ -9,6 +9,7 @@
>  #define PCI_DEVICE_ID_INTEL_HSW_U_IMC	0x0a04
>  #define PCI_DEVICE_ID_INTEL_BDW_IMC	0x1604
>  #define PCI_DEVICE_ID_INTEL_SKL_IMC	0x191f
> +#define PCI_DEVICE_ID_INTEL_SKL_U_IMC	0x190c
> 
>  /* SNB event control */
>  #define SNB_UNC_CTL_EV_SEL_MASK			0x000000ff
> @@ -64,6 +65,10 @@
>  #define NHM_UNC_PERFEVTSEL0                     0x3c0
>  #define NHM_UNC_UNCORE_PMC0                     0x3b0
> 
> +/* SKL uncore global control */
> +#define SKL_UNC_PERF_GLOBAL_CTL			0xe01
> +#define SKL_UNC_GLOBAL_CTL_CORE_ALL		((1 << 5) - 1)
> +
>  DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
> DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
> DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); @@ -179,6
> +184,60 @@ void snb_uncore_cpu_init(void)
>  		snb_uncore_cbox.num_boxes =
> boot_cpu_data.x86_max_cores;  }
> 
> +static void skl_uncore_msr_init_box(struct intel_uncore_box *box) {
> +	if (box->pmu->pmu_idx == 0) {
> +		wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
> +			SNB_UNC_GLOBAL_CTL_EN |
> SKL_UNC_GLOBAL_CTL_CORE_ALL);
> +	}
> +}
> +
> +static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) {
> +	if (box->pmu->pmu_idx == 0)
> +		wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0);
> +}
> +
> +static struct intel_uncore_ops skl_uncore_msr_ops = {
> +	.init_box	= skl_uncore_msr_init_box,
> +	.exit_box	= skl_uncore_msr_exit_box,
> +	.disable_event	= snb_uncore_msr_disable_event,
> +	.enable_event	= snb_uncore_msr_enable_event,
> +	.read_counter	= uncore_msr_read_counter,
> +};
> +
> +static struct intel_uncore_type skl_uncore_cbox = {
> +	.name		= "cbox",
> +	.num_counters   = 4,
> +	.num_boxes	= 5,
> +	.perf_ctr_bits	= 44,
> +	.fixed_ctr_bits	= 48,
> +	.perf_ctr	= SNB_UNC_CBO_0_PER_CTR0,
> +	.event_ctl	= SNB_UNC_CBO_0_PERFEVTSEL0,
> +	.fixed_ctr	= SNB_UNC_FIXED_CTR,
> +	.fixed_ctl	= SNB_UNC_FIXED_CTR_CTRL,
> +	.single_fixed	= 1,
> +	.event_mask	= SNB_UNC_RAW_EVENT_MASK,
> +	.msr_offset	= SNB_UNC_CBO_MSR_OFFSET,
> +	.ops		= &skl_uncore_msr_ops,
> +	.format_group	= &snb_uncore_format_group,
> +	.event_descs	= snb_uncore_events,
> +};
> +
> +static struct intel_uncore_type *skl_msr_uncores[] = {
> +	&skl_uncore_cbox,
> +	&snb_uncore_arb,
> +	NULL,
> +};
> +
> +void skl_uncore_cpu_init(void)
> +{
> +	uncore_msr_uncores = skl_msr_uncores;
> +	if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
> +		skl_uncore_cbox.num_boxes =
> boot_cpu_data.x86_max_cores;
> +	snb_uncore_arb.ops = &skl_uncore_msr_ops; }
> +
>  enum {
>  	SNB_PCI_UNCORE_IMC,
>  };
> @@ -544,6 +603,11 @@ static const struct pci_device_id skl_uncore_pci_ids[]
> = {
>  		PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCI_DEVICE_ID_INTEL_SKL_IMC),
>  		.driver_data =
> UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
>  	},
> +	{ /* IMC */
> +		PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCI_DEVICE_ID_INTEL_SKL_U_IMC),
> +		.driver_data =
> UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> +	},
> +
>  	{ /* end: all zeroes */ },
>  };
> 
> @@ -587,6 +651,7 @@ static const struct imc_uncore_pci_dev
> desktop_imc_pci_ids[] = {
>  	IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core
> ULT Mobile Processor */
>  	IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver),    /* 5th Gen Core U
> */
>  	IMC_DEV(SKL_IMC, &skl_uncore_pci_driver),    /* 6th Gen Core */
> +	IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core U
> */
>  	{  /* end marker */ }
>  };
> 
> --
> 2.4.0