RE: fsl-dcu not works on latest "drm-next"

From: Meng Yi
Date: Wed May 25 2016 - 06:25:37 EST

Hi Alexander,
Thanks for your reply.

> Commit d761701c55a99598477f3cb25c03d939a7711e74 only has one child
> commit in my repo. Both touch only i915 related things. Please do a proper
> bisect and name the offending commit. On which commit you got that
> backtrace BTW?
> From your backtrace I can't see anything related to regmap.

It is weird that using bisect, for the commit log is not linear.
I mean a newer date commit may be merged before an older date commit, when jump to that older date commit, the newer one will be lost, even though it is merged before older one.
So, I think it's difficult to use git bisect.
" d761701c55a99598477f3cb25c03d939a7711e74 " is just an older one, I mean between this commit and the next commit, maybe lots of commits are lost. So, it looks like this commit have nothing to do with the problem.

According to the backtrace, looks like the vblank interrupt is not happen or handled.
Then I found the irq is installed successfully, so the problem seems like the vblank irq is not properly setup. And here is the point , irq initia, irq handler and timing control code are using regmap.

I read out the value of relevant register using "CodeWarrior TAP", find that endianness is not right.

Then I changed endianness of the value to be written that using " regmap_write" . It works.
But "regmap_update_bits" still have the problem.

I had checked log of regmap, and didn't find which commit caused that.

Since I am not familiar with regmap, hope you can give me some advice.

Best Regards,
Meng Yi