Re: [PATCH] PCI/ASPM: fix reverse ASPM L0s assignment of upstream and downstream

From: Bjorn Helgaas
Date: Wed May 25 2016 - 14:33:26 EST

On Wed, May 25, 2016 at 02:19:01PM -0400, Sinan Kaya wrote:
> On 5/25/2016 1:50 PM, Bjorn Helgaas wrote:
> >> > You are saying that it is OK to enable L0s on just one side of the
> >> > link as long as both sides support L0s.
> > I'm not sure what you mean by the link parameters not being
> > compatible, but I think it is legal to enable L0s on only one
> > direction.
> I'm talking about L0s acceptable and entry latency times used to
> determine when L0s can be enabled.

Oh, I see. My understanding (again, I'm not a hardware person or a
PCIe spec expert) is that the latency numbers are an internal device
issue, not a PCIe link issue.

>From a PCIe point of view, I think we *could* enable L0s even if the
device's latency requirements wouldn't be met. The PCIe link itself
should work fine, but the device may have internal issues like FIFO

Of course, we want the device to work correctly, so we *shouldn't*
enable L0s if it would cause us to exceed the device's latency

It looks like the code enforces this by clearing bits in
link->aspm_capable (effectively pretending L0s or L1 are unsupported)
if the latency is too high.