Re: DRM DMA Engine

From: Daniel Vetter
Date: Thu May 26 2016 - 04:06:17 EST

On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
> Hi all,
> Currently I am trying to develop a DRM driver that will use
> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
> facing a difficulty regarding the understanding of the DRM DMA
> Engine. I looked at several sources and at the DRM core source
> but the flow of creating and interfacing with the DMA controller
> is still not clear to me.
> At DRI web page the X server is mentioned. Does it mean that the
> channel creation and handling is done by the X server? If so,
> what is the DRM driver responsible to do then and what exactly
> does the DRM core do? As I am using Xilinx VDMA do you foresee
> any special implementation details?
> Just for reference here is the description of the Xilinx VDMA:
> "The Advanced eXtensible Interface Video Direct Memory Access
> (AXI VDMA) core is a soft Xilinx Intellectual Property (IP) core
> providing high-bandwidth direct memory access between memory and
> AXI4-Stream video type target peripherals including peripherals
> which support AXI4-Stream Video Protocol." The driver is
> available at "drivers/dma/xilinx/xilinx_vdma.c".
> Another important point: I am using PCI Express connected to a
> FPGA which has all the necessary components (Xilinx VDMA, I2S,
> ...) and the HDMI TX Phy.
> Looking forward to you help.

If your dma engine is just for HDMI display, forget all the stuff you find
about DRI and X server on the various wikis. That's for opengl rendering.

The only thing you need is a kernel-modesetting driver, and nowadays those
are written using the atomic modeset framework. There's plenty of
introductory talks and stuff all over the web (I suggest the latest
version of Laurent Pinchart's talk as a good starting point).

> Best regards,
> Jose Miguel Abreu
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Daniel Vetter
Software Engineer, Intel Corporation