On 06/01/2016 06:26 PM, Santosh Shilimkar wrote:No worries. Am glad you got your setup working.
Yes and it works. The coherent memory space itself is beyond 4GB soSide note on LPAE:
For our current device tree and u-boot, LPAE is mandatory to bootup
for current Keystone boards - but this is not a SoC requirement,
booting without LPAE/HIGHMEM results in non-coherent DDR accesses.
This sounds like a regression, I thought we had this working when
keystone was initially merged and we got both the coherent and
non-coherent mode working with the same DT.
Hmm... True, I just tested next-20160602 with mem_lpae set to 0 in
u-boot and it seems to boot just fine.
I don't understand a requirement of having coherent memory without
Looks like a messed up description on my end, Looks like I have to
update my automated test framework to incorporate the manual steps