[tip:perf/core] perf/x86/intel: Change offcore response masks for Knights Landing

[tip-bot for Lukasz Odzioba]

Commit-ID:  9c489fce7a4a46c8a408e16e126bf3225401c7b5
Gitweb:     http://git.kernel.org/tip/9c489fce7a4a46c8a408e16e126bf3225401c7b5
Author:     Lukasz Odzioba <lukasz.odzioba@xxxxxxxxx>
AuthorDate: Mon, 16 May 2016 23:16:59 +0200
Committer:  Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Fri, 3 Jun 2016 09:40:17 +0200

perf/x86/intel: Change offcore response masks for Knights Landing

Due to change in register definition we need to update OCR mask:

MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14
MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38

Reported-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
Signed-off-by: Lukasz Odzioba <lukasz.odzioba@xxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Cc: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx>
Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Stephane Eranian <eranian@xxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: Vince Weaver <vincent.weaver@xxxxxxxxx>
Cc: akpm@xxxxxxxxxxxxxxxxxxxx
Cc: hpa@xxxxxxxxx
Cc: kan.liang@xxxxxxxxx
Cc: lukasz.anaczkowski@xxxxxxxxx
Cc: zheng.z.yan@xxxxxxxxx
Link: http://lkml.kernel.org/r/1463433419-16893-1-git-send-email-lukasz.odzioba@xxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
 arch/x86/events/intel/core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index ad08caf..0941f84 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -186,10 +186,8 @@ static struct event_constraint intel_skl_event_constraints[] = {
 };
 
 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7,
-			       MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x02b7,
-			       MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 	EVENT_EXTRA_END
 };