Re: Using irq-crossbar.c

[Lennart Sorensen]

On Mon, Jun 13, 2016 at 05:49:55PM +0200, Mason wrote:
> If I am not mistaken, the Cortex A9 MPCore GIC has 32 inputs.
> 
> So any SoC with more than 32 devices capable of generating IRQs
> would have to share interrupts, right?

No, you simply add another interrupt controller to cascade it.  That way
every device can still have one interrupt it owns.

One interrupt on the GIC is owned by the second interrupt controller,
and its driver determines which actual external interrupt occured.

It is only shared when there is no way to determine which device caused
a given interrupt to happen and you have to ask every one of the devices
sharing it if they caused it.

-- 
Len Sorensen