RE: [PATCH] cacheinfo: Introduce cache id

[Yu, Fenghua]

> From: Borislav Petkov [mailto:bp@xxxxxxx]
> Sent: Friday, July 01, 2016 11:40 AM
> On Fri, Jul 01, 2016 at 06:32:19PM +0000, Yu, Fenghua wrote:
> > We has prefix "L3" or "L2" in the syntax, id is for that level in each line.b
> 
> Give me a full example, please, how the id is going to be used.

Intel Cache Allocation Technology allows app to use only portion of L2 or L3 cache. Each cache has its own allocation MSR registers array which contains CBM (Cache Bit Mask) to specify which part of cache is allocated.

We have a user interface to allow user to input CBM bits to a specific cache MSR register array. In current kernel, there is no identification of the cache. So we propose the cache id to identify the cache.

So CAT user interface is called schemas which have multiple lines. Each line describes one cache allocation CBM (or schema).

For L3 schema on a two socket system which has two L3 caches, user input:
L3:0=3;1=f
That means user wants to allocate CBM 3 on L3 id 0 and CBM f on L3 id 1. Kernel gets this info and writes CBM 3 to one MSR register on the L3 cache with cache id 0 and write CBM f to one MSR register on another L3 cache with cache id 1.

User can allow a task to use this schema. When the task is running on a CPU that shares the L3 cache of cache id 0, the CBM 3 is used (via another PQR_MSR register pointing to the CBM) and a portion of the L3 of cache id 0 is allocated to the task and task can only uses that portion. When the task is scheduled on a CPU that shares the L3 cache of cache id 1, the CBM f is used and a portion of the L3 of cache id 1 is allocated to the task for use.

The current kernel has store cache info in cacheinfo structure and each cacheinfo eventually is exported in /sys/device/system/cpu/cpu#/cache/index#/. BUT....there is no existing identification methodology to allow user to specify a cache. CAT wants to allow user to use one id to specify which cache. That's the reason we propose the cache id in the patch.

Please note, socket# and core# and combination of them can not be used to identify a cache architecturally. A lot of machines have L3 per socket and L2 per core. BUT architecturally one socket can have more than one L3 and L2 can be shared by more than one core.

Thanks.

-Fenghua