Re: [PATCH v2] clk: Add fractional scale clock support

[Hoan Tran]

Hi Stephen,

On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@xxxxxxxxxxxxxx> wrote:
> Sorry I replied offlist before. Pressed the wrong key.
>
> On 06/30, Hoan Tran wrote:
>> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@xxxxxxxxxxxxxx> wrote:
>> >
>> > How is this different from clk-fractional-divider.c?
>> >
>>
>> This is a driver which clock output is multiplied with a fixed fractional
>> scale (denominator).
>> A field inside a register is used to configure the multiplier.
>>
>> Example: With fractional scale is 1/8.
>> Freq_out = Freq_parent * multiplier * (1/8)
>>
>> For fractional-divider, there are 2 fields of a register are used which
>>  - A field for numerator
>>  - A field for denominator
>> Freq_out = Freq_parent * numerator / denominator
>>
>
> Ok so the difference is that the denominator is a fixed value?

The major difference is a fixed denominator.
Another difference is:
In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below

Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.

> Perhaps that can be modeled as a clk-multiplier that is used as
> the only parent of a fixed divider?

Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
model as a clk-multiplier. And how to pass the fixed denominator into
a clk-multiplier.

> Or we can add a flag to the
> clk-fractional-divider code to handle this minor difference.

This driver is used 2 register fields for numerator, denominator and
calculates both of them.
Do you think I can integrate this fractional scale into it ?

Thanks
Hoan

>
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