[PATCH net-next 0/9] net: dsa: mv88e6xxx: STP and Global 2 cleanup

[Vivien Didelot]

The Marvell switches registers are organized in distinct internal SMI
devices, such as PHY, Port, Global 1 or Global 2 registers sets.

Since not all chips support every registers sets or have slightly
differences in them (such as old 88E6060 or new 88E6390 likely to be
supported soon), make the setup code clearer now by removing a few
family checks and adding flags to describe the Global 2 registers map.

This patchset has no functional changes except enabling basic STP
support and bridging on most chips when getting rid of a few
inconsistencies in chip descriptions (patch 1).

Next patchsets will introduce better description of other register maps.

Vivien Didelot (9):
  net: dsa: mv88e6xxx: remove basic function flags
  net: dsa: mv88e6xxx: split setup of Global 1 and 2
  net: dsa: mv88e6xxx: extract device mapping
  net: dsa: mv88e6xxx: extract trunk mapping
  net: dsa: mv88e6xxx: add cap for MGMT Enables bits
  net: dsa: mv88e6xxx: rework Switch MAC setter
  net: dsa: mv88e6xxx: add cap for PVT
  net: dsa: mv88e6xxx: add cap for Priority Override
  net: dsa: mv88e6xxx: add cap for IRL

 drivers/net/dsa/mv88e6xxx/chip.c      | 423 ++++++++++++++++++++--------------
 drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 149 +++++++-----
 2 files changed, 339 insertions(+), 233 deletions(-)

-- 
2.9.0