[PATCH 46/66] perf tools: Fallback to reading sysfs to get cacheline size

From: Arnaldo Carvalho de Melo
Date: Tue Jul 12 2016 - 18:42:54 EST


From: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>

On systems where sysconf(_SC_LEVEL1_DCACHE_LINESIZE) is not available,
such as musl LIBC and Android's bionic libc.

Cc: Adrian Hunter <adrian.hunter@xxxxxxxxx>
Cc: Chris Phlipot <cphlipot0@xxxxxxxxx>
Cc: David Ahern <dsahern@xxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Namhyung Kim <namhyung@xxxxxxxxxx>
Cc: Wang Nan <wangnan0@xxxxxxxxxx>
Link: http://lkml.kernel.org/n/tip-772obxzby758g7m2wmzcejxz@xxxxxxxxxxxxxx
Signed-off-by: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
---
tools/perf/perf.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/tools/perf/perf.c b/tools/perf/perf.c
index f7d7dbbd2af6..4b2ff021434c 100644
--- a/tools/perf/perf.c
+++ b/tools/perf/perf.c
@@ -497,6 +497,16 @@ void pthread__unblock_sigwinch(void)
pthread_sigmask(SIG_UNBLOCK, &set, NULL);
}

+#ifdef _SC_LEVEL1_DCACHE_LINESIZE
+#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
+#else
+static void cache_line_size(int *cacheline_sizep)
+{
+ if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
+ perror("cannot determine cache line size");
+}
+#endif
+
int main(int argc, const char **argv)
{
const char *cmd;
@@ -509,7 +519,7 @@ int main(int argc, const char **argv)

/* The page_size is placed in util object. */
page_size = sysconf(_SC_PAGE_SIZE);
- cacheline_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
+ cache_line_size(&cacheline_size);

if (sysctl__read_int("kernel/perf_event_max_stack", &value) == 0)
sysctl_perf_event_max_stack = value;
--
2.7.4