[PATCH 04/24] perf tools: Just pr_debug() about not being able to read cacheline_size

[Arnaldo Carvalho de Melo]

From: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>

So far the cacheline_size is only useful for the "dcacheline" --sort
order, i.e. if that is not used, which is the norm, then the user
shouldn't care that he is running this, say, on an Android system where
sysconf(_SC_LEVEL1_DCACHE_LINESIZE) and the
/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size sysfs file
isn't available.

An upcoming patch will emit an warning only for "--sort ...,dcacheline,...".

Cc: Adrian Hunter <adrian.hunter@xxxxxxxxx>
Cc: Chris Phlipot <cphlipot0@xxxxxxxxx>
Cc: David Ahern <dsahern@xxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Namhyung Kim <namhyung@xxxxxxxxxx>
Cc: Wang Nan <wangnan0@xxxxxxxxxx>
Link: http://lkml.kernel.org/n/tip-580cnkvftunyvt9n7unsholi@xxxxxxxxxxxxxx
Signed-off-by: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
---
 tools/perf/perf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/perf.c b/tools/perf/perf.c
index 4b2ff021434c..64c06961bfe4 100644
--- a/tools/perf/perf.c
+++ b/tools/perf/perf.c
@@ -503,7 +503,7 @@ void pthread__unblock_sigwinch(void)
 static void cache_line_size(int *cacheline_sizep)
 {
 	if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
-		perror("cannot determine cache line size");
+		pr_debug("cannot determine cache line size");
 }
 #endif
 
-- 
2.7.4