[PATCH] w1:omap_hdq: fix regression

[H. Nikolaus Schaller]

commit <e93762bbf681> ("w1: masters: omap_hdq: add support for 1-wire mode")
did add a statement to clear the hdq_irqstatus flags in hdq_read_byte().

If the hdq reading process is scheduled slowly or interrupts are disabled
for a while the hardware read activity might already be finished on entry
of hdq_read_byte(). And hdq_isr() already has set the hdq_irqstatus to
0x6 (can be seen in debug mode) denoting that both, the TXCOMPLETE
and RXCOMPLETE interrupts occurred in parallel.

This means there is no need to wait and the hdq_read_byte() can just read
the byte from the hdq controller.

By resetting hdq_irqstatus to 0 the read process is forced to be always
waiting again (because the if statement always succeeds) but the hardware
will not issue another RXCOMPLETE interrupt. This results in a false
timeout.

After such a situation the hdq bus hangs.

Signed-off-by: H. Nikolaus Schaller <hns@xxxxxxxxxxxxx>
---
 drivers/w1/masters/omap_hdq.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index a2eec97..bb09de6 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -390,8 +390,6 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
 		goto out;
 	}
 
-	hdq_data->hdq_irqstatus = 0;
-
 	if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 			OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
-- 
2.7.3