Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

[Borislav Petkov]

On Fri, Aug 19, 2016 at 03:34:22PM +0200, Peter Zijlstra wrote:
> Can't those events are NB events and cannot be used on per CPU counters.

It fugures, considering L3 is part of the NB on AMD.

So the Intel ones are special in the sense that they can be used on per
CPU counters even though they're not really per-CPU?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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