Re: [PATCH v2 8/8] gpio: Add Aspeed driver

[Linus Walleij]

On Fri, Aug 19, 2016 at 2:44 PM, Andrew Jeffery <andrew@xxxxxxxx> wrote:

> From: Joel Stanley <joel@xxxxxxxxx>
>
> The Aspeed SoCs contain GPIOs banked by letter, where each bank contains
> 8 pins. The GPIO banks are then grouped in sets of four in the register
> layout.
>
> The implementation exposes multiple banks through the one driver and
> requests and releases pins via the pinctrl subsystem. The hardware
> supports generation of interrupts from all GPIO-capable pins.
>
> A number of hardware features are not yet supported: Configuration of
> interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance
> for output ports.
>
> Signed-off-by: Joel Stanley <joel@xxxxxxxxx>
> Signed-off-by: Alistair Popple <alistair@xxxxxxxxxxxx>
> Signed-off-by: Jeremy Kerr <jk@xxxxxxxxxx>
> Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx>

This driver looks good now.

I guess I will have to wait for the rest to be fixed up
before applying.

Yours,
Linus Walleij