Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

[Peter Zijlstra]

On Wed, Aug 31, 2016 at 11:44:35AM +0100, Matt Redfearn wrote:
> Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
> architecturally defined ordering barrier. If a CPU does not implement it,
> the arch specifies that it must fall back to SYNC(0).
> 
> Define the barrier type and always use it in the pm-cps code rather than
> falling back to the heavyweight sync(0) such that we can benefit from
> the lighter weight sync.
> 

Changelog does not explain what 0x10 is, nor why its sufficient for this
case.

Changelog also fails to explain why you do this.

How do you expect anybody to review this?