Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

From: Matt Redfearn
Date: Wed Aug 31 2016 - 11:49:40 EST

On 31/08/16 15:28, Peter Zijlstra wrote:
On Wed, Aug 31, 2016 at 02:36:26PM +0100, Matt Redfearn wrote:
The code previously had 0x10 as a magic number, this patch just replaces
that with a #defined name. The value is documented in the MIPS64 instruction
set manual,, table 6.5.

This sync type has been standard since MIPSr2. That document also states
that "If an implementation does not use one of these non-zero values to
define a different synchronization behavior, then that non-zero value of
stype must act the same as stype zero completion barrier." As such,
stype_ordering can always be set to this sync type rather than setting it
only for certain CPUs.

Hi Peter,

Right. We all had a bunch of fun trying to decode that manual a while
back, and IIRC were left with a bunch of questions on what it all meant
in 3+ CPU scenarios.

Yes, I remember that fun....

In anycase, not sure why I was Cc'ed to this patch, but in general I

Patman decided to CC you as you've touched arch/mips/include/barrier.h I suppose.

have low confidence in barrier patches that lack lots of detail. And the
code in question has woefully inadequate comments:

/* Ordering barrier */
uasm_i_sync(&p, stype_ordering);

Order what against what and why? Is my first question. A comment really
should explain.

Fair enough - we'll put something together to improve the comments.

In any case, you've removed the only (runtime) assignment to the
variable, it can become 'const'.

True enough.