Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs structure
From: Madhavan Srinivasan
Date: Thu Sep 08 2016 - 20:45:16 EST
On Tuesday 06 September 2016 02:40 PM, Peter Zijlstra wrote:
On Tue, Sep 06, 2016 at 09:55:43AM +0530, Madhavan Srinivasan wrote:
What kind of information is this? I'm not familiar with the Power PMU
On Thursday 01 September 2016 12:56 PM, Peter Zijlstra wrote:
On Mon, Aug 29, 2016 at 02:30:46AM +0530, Madhavan Srinivasan wrote:
We have bunch of registers which exports information regarding the
It's a perennial request from hardware folks to be able to
How much and what is that? Can't we try and get interfaces sorted?
see the raw values of the pmu registers. Partly it's so that
they can verify perf is doing what they want, and some
of it is that they're interested in some of the more obscure
info that isn't plumbed out through other perf interfaces.
sampled instruction like SIER/SIAR/SDAR/MMCRA. Lot of bits in these
registers are not yet architected and incase of SIER register, some of
the bits are not plumbed out and we are working on getting some these
exposed via perf.
all that much, so you'll have to spell it out, not just mention the
registers its stuffed in.
Sure. When we profile for sample events,
SIER (Sampled Instruction Event Register) provides additional
information about the sampled event when PMI occurred.
SIER [41:42] indicates whether the SIAR(Sampled instruction address
and SDAR (Sampled data address register) are valid for the sampled event.
SIER [46:48] indicates the type of intructions,
001 Load Instruction
010 Store instruction
011 Branch Instruction
100 Floating Point Instruction other than a Load or Store instruction
101 Fixed Point Instruction other than a Load or Store instruction
110 Condition Register or System Call Instruction
SIER[49:51] gives information on the source of the sampled
instruction like instruction came from primary, secondary,
tertiary cache or beyond.
SIER[52:55] provide information on branch type instructions
Like mispredict and cause of it.
SIER[56:59] provides information on translation and also
source of translation like TLB, secondary cache, tertiary
SIER[60:62] provides the interesting data on the storage
access like L1/l2/L3... so on.
Most of these could be plumbed out through standard mechanisms
and it's all the other bits that are more interesting, but
these are not architected and not public.
Like wise, MMCRA (Monitor Mode Control Register A) is a
configuration register for sampling and thresholding events.
Provide data on various event configuration information.
Link to the PowerISA v2.07 and Chapters 9 describes in
detail on these registers.