Re: [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function

From: Linus Walleij
Date: Mon Oct 10 2016 - 03:59:11 EST

On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery <andrew@xxxxxxxx> wrote:

> The SPI1 function was associated with the wrong pins: The functions that
> those pins provide is either an SPI debug or passthrough function
> coupled to SPI1. Make the SPI1 mux function configure the relevant pins
> and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
> that were already defined.
> The notation used in the datasheet's multi-function pin table for the SoC is
> often creative: in this case the SYS* signals are enabled by a single bit,
> which is nothing unusual on its own, but in this case the bit was also
> participating in a multi-bit bitfield and therefore represented multiple
> functions. This fact was overlooked in the original patch.
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx>

Patch applied for fixes.

Linus Walleij