Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id

[Nilay Vaish]

On 10 October 2016 at 11:45, Luck, Tony <tony.luck@xxxxxxxxx> wrote:
> On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote:
>> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@xxxxxxxxx> wrote:
>> > From: Fenghua Yu <fenghua.yu@xxxxxxxxx>
>
>> > +               caches typically exist per core, but there may not be a
>> > +               power of two cores on a socket, so these caches may be
>> > +               numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
>> > +
>>
>> While it is ok that the caches are not numbered contiguously, it is
>> unclear how this is related to number of cores on a socket being a
>> power of 2 or not.
>
> That's a side effect of the x86 algorithm to generate the unique ID
> which uses a shift to put the socket number in some upper bits while
> leaving the "id within a socket" in the low bits.
>
> I don't think it worth documenting here, but I noticed that we don't
> keep the IDs within a core contguous either.  On my 24 core Broadwell
> they are not 0 ... 23 then a gap from 24 to 31.  I actually have on
> socket 0:
>
>  0,  1,  2,  3,  4,  5
>  8,  9, 10, 11, 12, 13
> 16, 17, 18, 19, 20, 21
> 24, 25, 26, 27, 28, 29
>

Thanks for the info.

--
Nilay