so that doesn't tell me a whole lot.It does to me! That cpu family is "broken" both on B0 and C0. I think that a CPU at 30% load should not have >31% branch misses. For example with 5% CPU usage you can't expect to get 10% branch-misses...
Well, Ontario is a small core and with the erratum workaround in place,Yes but on C0 I got better results. Maybe the BIOS vendor got similar results and did not apply the fix. They use the same BIOS for all machines B0, C0 and that could be the reason for not applying the 688 workaround.
it does get a bit worse too, apparently.
Hohumm, yeah, the workaround impacts the number of branch misses. ItThat is obvious. You can't say what it does, it might disable an internal buffer or force a CPU subsystem to run at a lower frequency, who knows?
probably disables some branch predictor optimization or so, which is
"problematic" in certain scenarios.
I guess we still want it because first we should not explode and then goExactly. I agree with that as I want to eliminate the crashes. Keep in mind that speed is something that all those APUs do not have and will never have, stability is what we are trying to improve.
fast :)
I'm thinking currently that if it is not easily triggerable, I couldNo problem, it is up to you. As I said above, I will not try to change your mind.
make the erratum workaround off by default and have a command line
option which people can enable in case they experience any of the
issues...