RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot

[Andrejczuk, Grzegorz]

> >  	init_intel_energy_perf(c);
> > +
> > +	/*
> > +	* Setting ring 3 MONITOR/MWAIT for thread
> > +	* when CPU is Xeon Phi Family x200 (KnightsLanding).
> > +	*/
> > +	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)
>
> Please move this conditional into the probe function.
>
> > +		probe_xeon_phi_r3mwait(c);
>
> Can you please check with your hardware people, whether this function is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID fault
> enable) is detectable via the PLATFORM_INFO MSR. I would be surprised if this thing is not detectable in some way.
>
> I really prefer detectable things over hardcoded crap which depends on model information.

I asked hardware people and MSR 0x140 should be called MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating that this bit can be set. 
Unfortunately hardcoded crap has to be used.