Re: [PATCH v2 2/2] x86/AMD: Group cpu_llc_id assignment by topology feature and family

[Yazen Ghannam]

> 
> > The NODEID_MSR feature only applies to Fam10h in which case the llc is at
> 
> s/llc/LLC (Last Level Cache/
> 
> Let's try to have abbreviations written out in their first mention in the text.
> 

Okay.

> > the node level.
> > 
> > The TOPOEXT feature is used on families 15h, 16h and 17h. So far we only
> > see multiple last level caches if L3 caches are available. Otherwise, the
> > cpu_llc_id will default to be the phys_proc_id. We have L3 caches only on
> > families 15h and 17h. On Fam15h, the llc is at the node level. On Fam17h,
> 
> s/llc/LLC/g
> 

Ack.

> > the llc is at the core complex level and can be found by right shifting the
>       ^^^
> 
> LLC
> 

Ack.

> > +
> > +		/*
> > +		 * We may have multiple LLCs if L3 caches exist, so check if we
> > +		 * have an L3 cache by looking at the L3 cache cpuid leaf.
> 
> x86 instructions in caps please: CPUID
>

Ack.
 
> > +		 */
> > +		if (cpuid_edx(0x80000006)) {
> > +			if (c->x86 == 0x15) {
> > +				/* LLC is at the node level. */
> > +				per_cpu(cpu_llc_id, cpu) = node_id;
> > +
> > +			} else if (c->x86 == 0x17) {
> 
> 				How about >= ?
>

This APICID format is only valid for Fam17h. What I'm going for is that
we fall back to a sensible default if we don't have a better assignment
for a new family. At first I thought that phys_proc_id would be good but
now I think node_id is better as a sensible default. I'll make this change
in the V3 set.

> 
> Btw, please add for your next submission:
> 
> Tested-by: Borislav Petkov <bp@xxxxxxx>
> 

For both patches?

Thanks,
Yazen