RE: [PATCH 2/2] perf/x86/intel/uncore: Fix SBOX support for Broadwell CPUs.

[Liang, Kan]

> This fixes SBOX support for Broadwell CPUs by checking the Power Control
> Unit CAPID4 register to determine the number of available SBOXes on the
> particular CPU before trying to enable them.
> 
> This patch has been tested on E5-2620 v4 (no SBOXes) and E5-2697 v4 (4
> SBOXes).
> 
> Signed-off-by: Oskar Senft <osk@xxxxxxxxxx>
> Tested-by: Mark van Dijk <mark@xxxxxxxxxxxx>


Reviewed-by: Kan Liang <kan.liang@xxxxxxxxx>


> Fixes: 3b94a891667c30fb4624221497d77fc65d950345
> ---
>  arch/x86/events/intel/uncore_snbep.c | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c
> b/arch/x86/events/intel/uncore_snbep.c
> index bcb54d7..6f4f67e 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -3054,13 +3054,26 @@ static struct intel_uncore_type
> *bdx_msr_uncores[] = {
> 
>  void bdx_uncore_cpu_init(void)
>  {
> +	int pkg = topology_phys_to_logical_pkg(0);
> +
>  	if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
>  		bdx_uncore_cbox.num_boxes =
> boot_cpu_data.x86_max_cores;
> -	uncore_msr_uncores = bdx_msr_uncores;
> 
>  	/* BDX-DE doesn't have SBOX */
>  	if (boot_cpu_data.x86_model == 86)
> -		uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
> +		bdx_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
> +	/* Detect systems with no SBOXes */
> +	else if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) {
> +		u32 capid4;
> +
> +		pci_read_config_dword(
> +			uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3],
> +			0x94, &capid4);
> +		if (((capid4 >> 6) & 0x3) == 0)
> +			bdx_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
> +	}
> +
> +	uncore_msr_uncores = bdx_msr_uncores;
>  }
> 
>  static struct intel_uncore_type bdx_uncore_ha = { @@ -3277,6 +3290,11
> @@ static const struct pci_device_id bdx_uncore_pci_ids[] = {
>  		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
>  		.driver_data =
> UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2),
>  	},
> +	{ /* PCU.3 (for Capability registers) */
> +		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fc0),
> +		.driver_data =
> UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
> +						   HSWEP_PCI_PCU_3),
> +	},
>  	{ /* end: all zeroes */ }
>  };
> 
> --
> 2.8.0.rc3.226.g39d4020