Re: [PATCH] perf/x86: fix event counter update issue

[Peter Zijlstra]

On Tue, Nov 29, 2016 at 02:46:14PM +0000, Liang, Kan wrote:
> > And note that we _ALWAYS_ set the IN bits, even for !sampling events.
> > Also note we set max_period to (1<<31) - 1, so we should never exceed 31
> > bits.
> > 
> 
> The max_period is 0xfffffffff.
> 
> The limit is breaked by this patch.
> 069e0c3c4058 ("perf/x86/intel: Support full width counting")
> https://patchwork.kernel.org/patch/2784191/
> 
> 	/* Support full width counters using alternative MSR range */
> 	if (x86_pmu.intel_cap.full_width_write) {
> 		x86_pmu.max_period = x86_pmu.cntval_mask;
> 		x86_pmu.perfctr = MSR_IA32_PMC0;
> 		pr_cont("full-width counters, ");
> 	}
> 

Wth do KNL/SLM have full_width_write set if they have short counters? I
should the whole point of the full_wdith thing was that in that case the
counters were actually 64bit wide.